In analog integrated circuits such as an integrated operational amplifier, the input offset voltage is an important performance specification. In an ideal differential amplifier, a common building block of operational amplifiers, when the difference between the two input signals is zero, the output is zero. However, a practical differential amplifier exhibits an unbalance caused by mismatches in the characteristics of the two input transistors. The input offset voltage is an error voltage that must be applied to the input terminals to balance the output voltage and overcome the effects of the transistor unbalances. The input offset voltage is added to an input signal at the amplifier's input terminals. This error voltage is a performance limiting aspect of all practical amplifiers. It is therefore a primary goal of precision analog integrated circuit design to minimize this input offset voltage.
For well-designed amplifiers the offset voltage is determined primarily by the mismatch of the transistor elements that make up the input differential pair.
FIG. 1 is an example of a folded-cascode, one stage operational amplifier comprising differential input transistors M1 (MOSFET or metal-oxide semiconductor field effect transistors) and M2 responsive respectively to differential input signals V1 and V2. The differential pair M1/M2 is subject to an offset voltage error as described above.
In addition to the differential input pair M1/M2, there are eight other transistors in FIG. 1 that work together to convert the differential input voltage at V1 and V2 into a single-ended output voltage at V3.
Transistors M7 and M8 are current sources whose current is determined by the current source I2 and the transistor gain relative to the diode connected reference transistor M3. Transistors M7 and M8 enable a reflection of the differential current flowing out of transistors M1/M2 into the active-load current mirror comprised of M9 and M10.
Transistors M4 and M5 control the voltage at the drain terminals of M1 and M2 so the amplifier can operate with a wide output voltage swing at V3. The transistors M3 and M6 provide voltage bias at the gate terminals of M7/M8 and M4/M5 respectively.
To insure that the input offset voltage of the amplifier shown in FIG. 1 is determined primarily by the mismatch between transistors M1 and M2, the transconductance of M7/M8 and M9/M10 must be substantially less than the transconductance of M1/M2. In practice this is not always possible. As such, all three differential pairs contribute to the input offset voltage of the amplifier shown in FIG. 1.
FIG. 2 shows differential NMOS transistors M1 and M2 and an input voltage source VOS in series with the gate node of the transistor M1. Voltage source VOS represents the error voltage associated with the input offset voltage that results from mismatches between the differential transistor pair comprising M1 and M2 in FIG. 2. Alternatively, it is equally acceptable to indicate the input pair offset in terms of an output offset current. Such a current is shown in FIG. 2 as IOS. IOS and VOS are related in that IOS is the difference between the drain currents of M1 and M2 when the gate terminals of M1 and M2 are shorted together. For a perfectly matched, differential pair, IOS would be equal to 0 A.
Amplifiers such as that in FIG. 1 are well known by those skilled in the art of analog integrated circuit design. Significant literature exists in the public domain to completely explain the operation of such an amplifier.
The mismatch of integrated elements manufactured according to a well-designed semiconductor process is a result of random manufacturing imperfections. These manufacturing imperfections include many factors such as lithography errors, process gradients, and chemical etching rate variations, among others.
For like-sized elements operated in identical environments on a single die, it is well understood that the distribution of mismatch exhibits a Gaussian or normal distribution. Such a relationship is more typically called a “bell-curve” distribution owing to the graphical shape of the distribution. The mathematics behind statistical manufacturing process distributions such as the normal distribution above is well documented in textbooks and research papers and well understood by those skilled in the art of analog integrated circuit design. Those works should be consulted for detailed explanations of statistical process distributions and the terms associated therewith.
An example of a typical Gaussian transistor mismatch distribution is shown in FIG. 3. While the data in FIG. 3 relates to MOS transistor mismatches, similar distributions are observed for other integrated electronic elements such as bipolar transistors, resistors, capacitors, and others. While the characteristic shape is similar, the standard deviation of the mismatch for other circuit components can vary greatly from that illustrated in FIG. 3 and for parameters other than voltage.
For example, integrated capacitors built using a modern CMOS semiconductor process using two layers of polysilicon for the capacitor plates achieve substantially greater matching for a given element area versus resistors of equal area. Additionally, MOS (metal oxide semiconductor) transistors match more poorly than resistors while bipolar transistors match substantially better than MOS transistors. Since the distribution of mismatch for bipolar transistors is less than that of MOS transistors, one typically finds precision low-offset voltage amplifiers built using bipolar transistors rather than MOS transistors.
To ensure a high manufacturing yield of a precision amplifier given a Gaussian manufacturing distribution of mismatch, a product designer generally designs assuming a 3 or 4-sigma standard deviation distribution of transistor mismatch. For the distribution shown in FIG. 3, the 3-sigma distribution of offset voltage mismatch is nearly 15 mV. Any amplifier designed with transistors that exhibit the mismatch distribution of FIG. 3 must anticipate at least a 15 mV initial input offset voltage prior to calibration.
Prior art techniques for post-manufacturing calibration of an analog integrated circuit entail the modification of an additional circuit element to aid in the final calibration of the performance specification. These additional circuit elements include among other things, resistive potentiometers, trimming capacitors, programmable resistor dividers, laser trim-able resistors, trim-able current sources, etc. These additional circuit elements not only add materials cost to the production of a system, but they also add labor costs since time is required to perform the calibration. Furthermore, if the circuit elements used for calibrating are not precisely the same as those used in the primary matching circuit, the performance of the calibration will degrade as operating environments change since dissimilar elements exhibit dissimilar drift characteristics. The magnitude of drift is generally related to the amount of initial offset prior to correction. It is preferred to have a minimum mismatch prior to calibration to insure that the drift is also minimized.
Fifteen-millivolts of input offset voltage is considered poor by those skilled in the art of precision analog amplifier design. Such a poor specification is not indicative of a high precision amplifier design. Furthermore, it is well understood by those skilled in the art that any calibration of such a large error will not be well maintained over environmental changes, such as time and temperature, during amplifier operation. As such, design techniques must be utilized to minimize the mismatch prior to calibration that in turn will minimize the post calibration drift.
It is well known by those skilled in the art of analog integrated circuit design that the typical mismatch observed between two integrated elements is inversely proportional to the square root of the area of the elements. In other words, the mismatch between one pair of elements that is four times larger than another pair can be expected to be better by a factor of 2, the square root of 4. Therefore, one important design technique to minimize the mismatch of a differential transistor input pair is to make the structures physically large.
However, using a large physical structure on a silicon die is an expensive solution to achieve matching since this adds materials cost. In many cases it further degrades other equally important performance specifications. For example, as the size of a physical structure increases so does the parasitic capacitance of the same structure. In the case of a resistor, this higher capacitance lowers the bandwidth of the resistor and hence the bandwidth of an analog circuit employing the resistor. Many times the bandwidth of an analog circuit is nearly as important as the matching requirements; therefore tradeoffs must be made between matching and bandwidth during the design phase.
FIG. 4A shows a top-down view of a MOS transistor, including drain, source, gate, and body regions. The transistor exhibits one source of mismatch error in MOS transistors; random channel length variations. FIG. 4B shows a cross-sectional view of the same MOS transistor taken along the plane 4B.
When the gate electrode of a MOS transistor is formed during manufacturing, a multiplicity of random error-generating events occur such that the gate electrode is not formed with a perfectly flat edge along the width of the MOS channel. These random events include, among other things, photolithographic errors and gate electrode etching rate variations. A MOS transistor with a non uniform gate electrode edge will exhibit a varying channel length across the width of the MOS transistor. Random channel length variations directly affect MOS transistor threshold voltage.
The depiction of the transistor mismatch error source shown in FIGS. 4A and 4B is greatly exaggerated and an over simplification of the manufacturing anomalies that lead to mismatched performance between identically sized MOS transistors manufactured simultaneously. There are numerous other manufacturing abnormalities that contribute to the mismatch of MOS transistors. Two other such abnormalities include random fixed charge variations in the gate oxide underneath the gate electrode and random variations in drain/source lateral diffusion profiles.
It is the accumulation of all manufacturing error sources during MOS transistor manufacturing that result in MOS transistor pair mismatch. When a chart such as that shown in FIG. 3 is presented, it is normally assumed by those skilled in the art that the distribution depicted includes all mismatch error sources, not only MOS channel length variation.
FIG. 5 shows how two randomly mismatched MOS transistors would be interconnected to form an input differential pair such as the input pair shown in FIG. 1 and FIG. 2. The circuit interconnection shown in FIG. 5 constitutes a mismatched pair of MOS transistors.
FIG. 5 also shows the input offset voltage error source VOS and the equivalent current error source IOS. FIG. 5 is a physical depiction of the electrical schematic shown in FIG. 2 and is intended to represent a practical, albeit simplistic, example of mismatch found in modern MOS analog amplifier products.
An object of integrated analog amplifier design is to minimize mismatch errors such as those shown in FIG. 5. A prior art technique to achieve such a minimization is to build M1 and M2 as physically large structures on the silicon die, as described above. It is well understood by those skilled in the art of analog amplifier design that the improvement factor achievable by using large MOS transistors is inversely proportional to the square root of the increase in gate area of the transistor. In simpler terms, matching improves as transistors become larger.
FIG. 7 shows one MOS transistor that is divided into four equal sized transistors. One could manufacture two separate transistors from the four individual transistors by permanently connecting in parallel the transistors with gates 1 and 3 and connecting in parallel the transistors with gates 2 and 4. This is a prior art example of building transistors from a multiplicity of transistors that are permanently interconnected interdigitally across the surface of a silicon wafer. As the gate regions increase in size, the matching of the transistors would be expected to improve. While a depiction of only four transistor segments is shown in FIG. 7, one can expand the above technique to include any practical number of segments.
In a similar manner as described above, one could arrange the divided transistors in FIG. 7 into a square of two-by-two transistors rather than a rectangle of one-by-four as presently shown. The four transistors could then be permanently interconnected in the form of an “X” where the top left and bottom right transistors form one transistor and the top right and bottom left transistors form the second. This is another prior art technique to minimize transistor mismatch and is commonly referred to by those skilled in the art as cross-coupling transistors.
Cross-coupling and interdigitization are prior art techniques used to minimize mismatch that results from manufacturing anomalies that occur as processing gradients in addition to localized random errors.
Prior art techniques also utilize time domain techniques to minimize the effects of statistical mismatch. A chopper-stabilized amplifier is a prior art technique that employs a continuous digital clock signal applied to the mismatched elements in a prescribed fashion such that the average mismatch is driven to zero. Chopper-stabilized amplifiers are well known by those skilled in the art of amplifier design. Significant literature exists in the public domain to fully explain the operation of such amplifiers.
Similar to chopper stabilization, sampled data analog systems such as a pipelined analog to digital converter, utilize a concept known as dynamic element matching (DEM) to overcome element mismatch.
While time averaging solutions such as DEM and chopper stabilization are able to theoretically mask all vestiges of element mismatch in an analog circuit, many precision amplifier applications cannot tolerate the byproducts of a clock signal injected into the signal path. Two intolerable byproducts are long overload recovery time when the amplifier is driven into saturation and the introduction of switching noise into the signal path. Additionally, errors that drift faster than the amplifiers response time are not eliminated and therefore add error to the output in a manner similar to that produced by element mismatch. The present invention provides many of the benefits inherent in a time-averaging solution without introducing the deleterious effects listed above.
While not strictly a matching circuit solution, Flynn, et al., “Digital Calibration Incorporating Redundancy of Flash ADCs,” May 2003, IEEE Transactions on Circuits and Systems, Vol. 50, No. 5, pp. 205-213, describes a calibration scheme whereby a group of elements are present in a system and the one element that has the prescribed level of performance is enabled into the circuit. This is similar to a manufacturing scheme whereby parts are “cherry-picked” before they are assembled into the final system. Cherry-picking is slang used to describe the process of investigating the performance of each element in a group and then selecting that one element that exhibits the best performance.
Cherry-picking is an extremely inefficient and costly solution in that a multiplicity of completed elements must be included on the die with the end result that only one will be utilized.
Summarily, electrical circuit element type, size, and location as well as cherry-picking parts and the introduction of an averaging clock signal are all prior art methods to manage input offset voltage errors. The present invention provides new methods that enable the use of smaller matching elements with less regard for element type, location, and circuit application, thereby improving the performance and lowering the production costs of analog integrated circuits.